Power Domain Aware DFT Implementation

Power awareness has become an important dimension for recent advances in VLSI. Multiple functional power domains (PD) are forcing Design-for-Test (DFT) designers to adjust DFT insertion and implementation to comply with IEEE 1801 correctness. Several challenges emerge for DFT tools and engineers, including but not restricted to a) additional low power cells inserted & crossings created due to DFT connections, b) power aware scan chain connection with optimal scan wirelength, and c) ensuring Unified Power Format (UPF) correctness post DFT insertion. This paper describes power domain aware DFT techniques for core wrapping, heterogenous fanouts and PD fencing aware scan chain stitching. A correct by construction approach results in fewer low power cells, improved scan wirelength & fewer IEEE 1801 rule violations. The EDA automation demonstrated in this paper reduces the manual overhead for chip designers to ensure power correctness of the design after DFT implementation.