All-van der Waals stacking ferroelectric field-effect transistor based on In 2 Se 3 for high-density memory

High-density integration of ferroelectric field-effect transistors (FeFETs) is hindered by factors such as interfacial states, short-channel effects, and ferroelectricity degradation in ultrathin films. Accordingly, the introduction of two-dimensional (2D) materials could effectively solve these problems. However, most current studies focus on the replacement of Si-based channels with 2D channels. Little progress has been made in addressing issues caused by bulk-phase ferroelectric gate layers, such as the unavoidable rough interfaces and the fading of ferroelectricity in ultrathin films. Herein, the 2D ferroelectric material In 2 Se 3 is introduced as the gate dielectric. Combined with 2D insulating h-BN and 2D channel MoS 2 , an all-van der Waals (vdW) stacking FeFET is fabricated to provide a straight solution for the abovementioned issues. First, the robust ferroelectric phase of In 2 Se 3 is verified in an ultrathin film case and a high-temperature case, which is outstanding among recently reported 2D ferroelectrics. Second, device-level out-of-plane ferroelectric polarization switching is achieved in the cross-structure device. Based on these results, In 2 Se 3 is adopted as the ferroelectric gate dielectric to fabricate all-vdW stacking FeFETs. The subsequent transistor performance measurement on the fabricated FeFETs indicates that the ferroelectric polarization of the In 2 Se 3 layer plays a dominating role in forming a counterclockwise hysteresis loop. Further pulse response measurements manifest the feasibility of nonvolatile channel conductance tuning of these devices with a proper pulse design. Our findings suggest that In 2 Se 3 is a suitable 2D ferroelectric gate material and that all-vdW stacking FeFETs based on 2D ferroelectrics are promising in the application of high-density memory.