Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

G. Tsutsui,S. Song,J. Strane,R. Xie, L. Qin,C. Zhang, D. Schmidt,S. Fan, B. Hong,Y. Jung,C-W. Sohn,I. Hwang,J. Yim, G. H. Son, G. Jo,K-I. Kim,M. Sankarapandian,S. Mochizuki,I. Seshadri,E. Miller, J. Li,J. Demarest,C. Waskiewicz,R. G. Southwick, H. Zhou,R. N. Pujari, P. Nieves,M. Wang,H. Jagannathan,B. Anderson,D. Guo,R. Divakaruni,T. Wu,K-I. Seo,H. Bu

2022 International Electron Devices Meeting (IEDM)（2022）

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关键词

40CGP VTFET ring oscillator,CMOS technology,contacted gate pitch,DC performance,effective capacitance,hardware based performance assessment,logic area,size 45.0 nm,technology target,vertical-transport FET,vertical-transport nanosheet technology

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