Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

Vertical-transport FET (VTFET) is a strong candidate for future CMOS technology. The concept of VTFET has been demonstrated in our previous report, which enables to scale logic area beyond sub-45nm contacted gate pitch (CGP). This paper focuses on performance assessment of VTFET based on hardware (HW). 1. 2x effective capacitance $(\mathrm{C}_{\mathrm{e}\mathrm{f}\mathrm{f}})$ contrasting to technology target is demonstrated based on 40CGP VTFET ring oscillator. Two major bottlenecks are identified as DC performance $(\mathrm{I}_{\mathrm{e}\mathrm{f}\mathrm{f}}$ at target $\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$) detractor. 90% DC performance compared to the target has been demonstrated by resolving the bottlenecks.