A 12-Bit 1gs/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration

Current-steering DACs are known to be suitable for wideband applications owing to the fast current switching with differential switches and the low output load resistance [1] –[6]. In current-steering DACs, mismatches between the current sources(CS) are the major source of nonlinearity. To reduce the CS mismatch effect, previous works often utilized the Dynamic Element Matching (DEM) [1], [4] or current-source calibration techniques [2], [3], [5], [6]. The DEM randomizes the DAC switching to spread the mismatch tones as noise to improve the SFDR at the expense of increased noise floor, deteriorating the SNR. Background calibration techniques do not have the noise floor issue as they reduce the CS mismatch directly with PVT insensitivity. However, the periodic CS switching operations, disengaging for calibration and reengaging for normal operation, generate unwanted calibration spurs. These spurs can be also randomized as in [6], but the technique still has a disadvantage of increased noise floor near the calibration frequency.