29.3 an 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees
2023 IEEE International Solid-State Circuits Conference (ISSCC)（2023）
关键词
2.5× area increase,bit-sparsified sign-magnitude multiplications,central MAC units,computational complexity,energy consumption,Fig. 29.3.1 center,gate-level simulations,general purpose computing,high-efficiency neural accelerator engines,modest energy improvement,neural computation,neural networks,normally distributed operands,previous neural engines,sign bits,sign-magnitude multiplication,sign-magnitude number representation,significant overhead,SM addition,SM multiplication,SM representation,subtraction,uniformly distributed operands
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