A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement

Woongrae Kim, Chulmoon Jung, Seongnyuh Yoo,Duckhwa Hong,Jeongjin Hwang,Jungmin Yoon, Ohyong Jung, Joonwoo Choi,Sanga Hyun,Mankeun Kang,Sangho Lee,Dohong Kim,Sanghyun Ku, Donhyun Choi,Nogeun Joo, Sangwoo Yoon, Junseok Noh,Byeongyong Go, Cheolhoe Kim, Sunil Hwang, Mihyun Hwang, Seol-Min Yi, Hyungmin Kim,Sanghyuk Heo,Yeonsu Jang, Kyoungchul Jang,Shinho Chu, Yoonna Oh,Kwidong Kim, Junghyun Kim,Soohwan Kim,Jeongtae Hwang,Sangil Park, Junphyo Lee,Inchul Jeong,Joohwan Cho,Jonghwan Kim

ISSCC（2023）

引用 0|浏览8

暂无评分

关键词

active addresses,core-bias modulation,DRAM products,DRAM resilience,DRAM row,DRAM security,DRAM technology node scaling,multistep precharge,multistep precharge reinforces intrinsic row-hammer tolerance,per-row hammer tracking,per-tow hammer tracking,PRHT,probabilistic-aggressor tracking,probabilistic-aggressor-tracking scheme,refresh retention time,refresh-management function,refresh-management functionality,refresh-management schemes,reliability enhancement,RFM,row hammer attacks,row hammer tolerance,row-hammer-protection,security enhancement

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要