Design Strategies for High-resolution High-speed Flash-assisted Pipelined SAR ADCs.
2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)（2022）
Abstract
A preliminary study performed before the transistor level simulations of converters with challenging specifications is presented. The target converter is a pipelined SAR ADC with 18-bit resolution that operates with a conversion rate larger than 10 MS/s. Various techniques are proposed for reducing the number of SAR conversion cycles. A foreground interstage gain error calibration method is also discussed.
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Key words
converter transistor level simulations,foreground interstage gain error calibration method,high-resolution high-speed flash-assisted pipelined SAR ADC,SAR conversion cycles
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