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High Performance Injection-Locked PLL Architectures: An Overview

Zhaoji Jin,Ting Yi

2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)(2022)

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摘要
Low jitter phase locked loops (PLL) are widely used as clock generators and play a very critical role in various applications such as serial link or data converter systems. On the basis of conventional PLLs, researchers have invented sub-sampling, injection locking, and other techniques to improve the performance of PLL with constrained power and area. The injection-locked PLL (ILPLL) reduces the clock jitter by eliminating the accumulated jitter periodically. Because of the simple structure, the ILPLL has become the research focus in recent years. This paper reviews the development and application scenarios of ILPLLs.
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关键词
injection-locked phase-locked loop,PLL,phase noise,jitter,sub-sampling phase-locked loop
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