Absolute overlay measurements based on voltage contrast defect inspection with programmed misalignments for DRAM devices

Improvements on on-cell overlay is necessary to suppress misalign induced defects. Precise and accurate on-cell overlay measurements are strongly demanded, however, we are facing limitations on conventional CD-SEM based on-cell overlay measurements, such as unexpected overlay bias. To mitigate drawbacks of top view based on-cell overlay measurements, we present voltage contrast based overlay measurements (VCBO) which utilize specially designed cell patterns with combinations of programmed misalignments on scribe lanes, measured by defect inspection equipment, eP5 [1]. We successfully demonstrate the first defect based overlay measurement on DRAM device and a potential of 27% in-die overlay gain is shown. Also, we display overlay process margin at about similar to 1000 points on wafer. As a definite standard of on-product overlay measurement, this technology will be used for advanced misreading correction (MRC). We believe that the technique would be widely used and become necessary in near future.