Single-Event Evaluation of Xilinx 16nm UltraScale+™ Single Event Mitigation IP

This paper presents the single-event upset (SEU) response of the Xilinx Soft Error Mitigation (SEM) IP as applied to Xilinx 16nm UltraScale+ MPSoC. The SEM IP is a solution to detect, correct, and classify single event upsets (SEU) in configuration memory (CRAM) of Xilinx FPGAs. Data obtained from accelerated test using a 64MeV mono-energetic proton source is compared to control static readback test data in order to evaluate the SEM IP capability to detect and correct SEU. Results show that 100% of events are detected and the IP FIT is ≪ 1 FIT at NYC sea level. In addition, the SEU response of Xilinx 16nm 3D IC stacked silicon on interposer (SSI) technology is also characterized using a XCVU9P device. SEU and multiple bit upset (MBU) results are also presented.