MOL Patterning Challenges in Scaled SRAM with Vertical Surrounding Gate Transistors (SGT)

The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.