A 4.0 Μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range
IEEE transactions on electron devices/IEEE transactions on electron devices(2022)
Abstract
It is anticipated that ubiquitous computer vision (CV) and artificial intelligence (AI) applications used on mobile devices will grow significantly. Such applications require battery-powered, always-on mobile devices to support indoor/outdoor, day/night usages. A global shutter (GS), stacked digital pixel sensor (DPS) is a promising candidate to meet such requirements because of its potential for ultralow-power, ultrahigh dynamic range (HDR), and a small form factor. This article presents a prototype 4.0- ${\mu } \text{m}$ stacked DPS operating in its dual quantization (2Q) to realize HDR. The 4.0- ${\mu }\text{m}$ DPS pixel is formed with two layers, a backside illuminated pinned photodiode (PD) pixel on the top layer and an in-pixel analog-to-digital conversion (ADC) circuit with 9-bit static random access memory (SRAM) on the bottom layer. A Cu-to-Cu hybrid bonding (HB) technology is used to connect the two layers via pixel-level interconnect. In the 2Q scheme, a time-stamp (TS) quantization and a linear ADC are performed sequentially in the same frame, which extends the dynamic range (DR) with a small number of ADC bits of 9. The DPS with a 1024 $\times$ 832 pixel array has achieved a single-exposure ultra HDR of 107 dB in a single frame. The nonlinear conversion characteristic of the TS mode provides an equivalent full well capacity (FWC) of 2000ke − , while the noise floor in the linear ADC mode is 8.3e − .
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Key words
Quantization (signal),Random access memory,Dynamic range,Codes,Voltage,Logic gates,Image coding,CMOS image sensor (CIS),computer vision (CV) sensor,digital pixel sensor (DPS),global shutter (GS),high dynamic range (HDR),noise analysis,stacked process
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