Hardware Acceleration of Bayesian Network based on Two-dimensional Memtransistors

Long before Bayes proposed his landmark theorem on the probability of an event, based on prior knowledge of other events, natural intelligence has adopted Bayesian inference as a tool to ensure survival for almost all species. The fact that living beings must make critical decision for finding food, avoiding predators, and locating mates, based on information gathered by their sensory organs with limited sensitivity and under noisy surroundings, emphasizes the importance of probabilistic computing for evolutionary success. While the anatomy of neural hardware that accomplishes such task is far from being known, it is clear that stochastic computing is a fundamental aspect of natural intelligence, and Bayesian networks (BNs) are powerful mathematical constructs for the same. Interestingly, BNs also find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc. While the concept of BN is well known, there are very limited hardware realizations of BN. CMOS [1, 2] based BNs require massive hardware resources (thousands of transistors), whereas, memristor [3-5] and spintronics [6-8] based BNs necessitate hybrid design with CMOS peripherals limiting the area and energy efficiency [9]. Here, we circumvent these challenges by introducing a compact and low-power BN architecture embedded in memory based on 2D memtransistors.