Improving Failure Analysis for Cell-Internal Defects through Cell-Aware Technology

Abstract This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.