High Speed and Low Power Error Recovery Approximate Multiplier for Image Processing Appliclations

Abstract In approximating, the requirement for accurate results is ignored because of some other applications with better performance in terms of area or delay. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). Here in this paper we propose an approximate multiplier circuit with two various architectures where one is designed by modifying the design of the circuit by adding AND-OR logic approximation in the partial product generation stage and a dual quality adder at the final stage of the multiplication for error recovery. The other one is by adding the same AND-OR logic approximation in the partial product reduction stage where it is applied tow only least significant part and accurate adders are used in the remaining for final outcome. In addition, many errors make little noticeable variations in practice, for instance image processing owing to human perceptual restrictions. Error-tolerant algorithms and their utilization inspired the progress of inexact multipliers which trade-off between power efficiency, area and speed. The proposed approximate multipliers have been shown that both have a lower area and one with better accuracy and error recovery other with delay than an exact Wallace multiplier and existing approximate designs. Functional analysis has shown that on a statistical basis, the proposed multipliers have considerable error distances and thus, they achieve a high accuracy and better area. To show the effectiveness of the work we had implemented and image processing application with the help of Xilinx System generator. The total designs are done and implemented in Xilinx ISE 14.7 with Verilog HDL coding.