A Transistor-Level DFF Based on FinFET Technology for Low Power Integrated Circuits

Jun Wang, Haozhou Zhu,Yang Yu, Xu Liu,Eryuan Feng, Chuanzhen Lei,Yanfei Cai,Hao Zhu,Qing-Qing Sun,David Wei Zhang

IEEE Transactions on Circuits and Systems II: Express Briefs（2022）

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关键词

Latches,Logic gates,Libraries,Delays,Transistors,Standards,FinFETs,FinFET,low power design,leakage reduction,scan D flip-flop,transistor-level gate length biasing

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