VeriGOOD-ML: an Open-Source Flow for Automated ML Hardware Synthesis

Hadi Esmaeilzadeh,Soroush Ghodrati,Jie Gu,Shiyu Guo,Andrew B. Kahng,Joon Kyung Kim,Sean Kinzer,Rohan Mahapatra,Susmita Dey Manasi,Edwin Mascarenhas,Sachin S. Sapatnekar,Ravi Varadarajan,Zhiang Wang,Hanyang Xu,Brahmendra Reddy Yatham,Ziqing Zeng

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)（2021）

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关键词

design planning approach,ML platforms,VeriGOOD-ML,nonDNN ML algorithms,ML benchmarks,automated ML hardware synthesis,machine learning algorithm,back-end design flow,Pareto-optimal-PPA back-end implementations,TABLA platform,dataflow architecture,GeneSys platform,systolic array,SIMD array,Axiline approach

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