A Low-Noise CTIA-based pixel with CDS for SWIR Focal Plane Arrays

This paper proposes a readout integrated circuit (ROIC) pixel for short-wavelength infrared (SWIR) focal plane arrays, including an in-pixel capacitive trans-impedance amplifier (CTIA) with correlated double sampling (CDS) circuit. An inverter-based operational amplifier is proposed, which can obtain higher gain under the same power consumption, thereby effectively reducing thermal noise. At the same time, a compact in-pixel CDS is proposed, which uses fewer switches to reduce the pixel area. This pixel circuit is designed in 180nm 1P5M CMOS process. The simulation result shows that the output swing of the circuit is 1.2V, and the linearity within the output swing reaches 99.9% The integrating capacitor is 8fF, and the pixel output noise after CDS is 11.38e-, which is 48% lower than the traditional CTIA circuit.