Altered EEG Microstates During Motor Preparation for Resting-State, Voluntary and Instructed Conditions

Power Consumption of a 64 K bit SRAM using increased substrate bias 7 T SRAM cell is computed using 90nm_CMOS Technology on Cadence Virtuoso Tool. Major part of this work is reducing power consumption and it is obtained for 1 K bit, 2K bit, 4K bit, 16 K bit, 32 K bit and 64 K bit SRAM blocks. The outcome of the different SRAM blocks designed using 7 T SRAM cell are compared with 6 T SRAM cell SRAM blocks in terms of power consumption. The experimental results show improved performance of increased substrate bias 7 T SRAM Cell over 6 T SRAM Cell at reduced power consumption.