A Novel Foundry Yield Model Using Critical Area Analysis

Xiaoyuan Qi,Uwe Schroeder,Aaron Sinnott,Binod Kumar G. Nair, Akif Sultan,Sriram Madhavan,Jac Condella,Jonathan Fales,Jeffrey Nelson,Frank Gennari, Ya-Chieh Lai,Rwik Sengupta,Philippe Hurat

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING（2021）

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Integrated circuit modeling,Semiconductor device modeling,Probes,Companies,Circuit faults,Analytical models,Systematics,Yield estimation,critical area,modeling,logic,memories

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