A New Asynchronous Pipeline Architecture of Support Vector Machine Classifier for ASR System

In this paper, it is proposed an asynchronous pipeline architecture for Support Vector Machine (SVM) non-linear classifier in Field Programmable Gate Array (FPGA) - INTEL-ALTERA prototyping where the training dataset was generated from a Hybrid Training Algorithm implemented in Matlab Software. Such an algorithm is composed from a Particle Swarm Optimization (PSO) algorithm application followed by the SVM Training. For the speech signal pre-processing part, techniques of Mel-frequency Cepstral Coefficients (MFCCs) extraction and Discrete Cosine Transform were used. The whole idea was to develop an Automatic Speech Recognition (ASR) System with minimum use of area as possible, low power consumption and with minimum human intervention. The results were obtained from 109.95mW of power consumption, 5% of used LUTs and 99% of accuracy in recognition success rate.