On-chip Adaptive Matching Learning with Charge-Trap Synapse Device and ReLU Activation Circuit

For the hardware implementation of artificial intelligence, neuromorphic systems have major advantages in terms of their energy consumption and massively parallel operation compared to conventional computing systems. For general-purpose neuromorphic systems, the on-chip learning of large-scale deep neural networks (DNN) is an essential function. However, compared to a backpropagation algorithm of DNN, an on-chip learning technology, which can be efficiently implemented in hardware without accuracy degradation, has not yet been developed. Consequently, off-chip learning-based neuromorphic systems that perform only inference operations are a promising approach to the first step in the commercialization of neuromorphic systems. To address the limitation of off-chip learning that cannot cope with real-time errors, we proposed on-chip adaptive matching learning (AML). By adding a spare single-layer neural network where an on-chip AML was carried out in parallel to the main neural network, it was possible to implement an adaptive neuromorphic system that can correct errors during real-time applications. For hardware implementation, we proposed a synapse device, synapse array, and neuron circuit. Finally, we conducted a system-level simulation of the adaptive neuromorphic system to verify the feasibility of the proposed on-chip AML.