A Leading-Edge 0.9 Mu M Pixel Cmos Image Sensor Technology With Backside Illumination: Future Challenges For Pixel Scaling (Invited)

Pixel scaling trend on CMOS image sensor (CIS) calls for a novel technology to improve sensor's optical response being blocked or interfered by metal layers in traditional front-side illumination (FSI) sensor structure. Recently, backside illumination (BSI) sensor technology gradually becomes the main-stream CIS process to achieve virtually 100% fill-factor to boost the optical response and enhance optical angular response due to a shorter optical path. In this paper, a leading-edge N65 0.9 mu m pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges for pixel-size scaling beyond 0.9 mu m are discussed.