A 129.5-151.5Ghz Fully Differential Power Amplifier in 65nm CMOS

This paper presents a 129.5-151.5GHz fully differential power amplifier in 65nm CMOS process. The power amplifier constitutes a two-stage neutralized amplifier and an one-stage cascode amplifier. The neutralized amplifier is employed to improve the gain and isolation of the power amplifier, and the cascode structure is mainly used to improve the output power. The post-layout simulation results show that PA realizes a small signal gain of 10.5dB at the frequency of 139GHz, and the 3dB bandwidth of 22GHz, with a saturated output power of 9dBm, and this power amplifier supports modulation of OOK signal with 20Gbps transmission rate.