12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications

This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for a Bluetooth Low Energy (BLE) application. The objective of this work is to reduce the number of capacitors in the Capacitor Digital to Analog Converter (CDAC). To achieve this, a hybrid type DAC has been applied where 8 Most Significant Bits (MSB)s are decided through capacitive DAC and 4 Least Significant Bits (LSB)s are decided in a Resistor DAC (RDAC). The conversion speed for this design reaches up to 6 MS/s. The prototype ADC is designed in a 90 nm complementary metal-oxide semiconductor (CMOS) process. The analog and digital supply voltage range for this design are 2.7-5.5 V and 1.1-1.3 V respectively. For 6 MS/s conversion rate, this ADC achieves up to 11.8 and 11.2 effective number of bits (ENOBs), for maximum and minimum supply voltages respectively. The current consumption from a 5 V supply voltage is 980 mu A and the Figure of Merit (FOM) is 229 fJ/Conv.step.