Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores
2021 IEEE International Symposium on Circuits and Systems (ISCAS)（2021）
Key words
code size,software emulation minimizes,hardware cost,area-optimized,IEEE 754-compliant RISC-V FPU,Tiny-FPU,energy efficiency,MCU-class processor,double precision versions,single-precision versions,double singleprecision FPU,low-cost floating-point support,small RISC-V MCU,Internet-Of-Things domain,floating-point arithmetic,efficient hardware floating-point units,FPUs
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