A 14 nm Embedded STT-MRAM CMOS Technology

D. Edelstein,M. Rizzolo,D. Sil,A. Dutta,J. DeBrosse, M. Wordeman,A. Arceo, I. C. Chu,J. Demarest,E. R. J. Edwards, E. R. Evarts, J. Fullam,A. Gasasira,G. Hu, M. Iwatake, R. Johnson, V Katragadda,T. Levin, J. Li,Y. Liu, C. Long,T. Maffitt,S. McDermott,S. Mehta, V Mehta,D. Metzler,J. Morillo, Y. Nakamura,S. Nguyen, P. Nieves, V Pai,R. Patlolla,R. Pujari,R. Southwick,T. Standaert,O. van der Straten,H. Wu,C-C Yang,D. Houssameddine, J. M. Slaughter,D. C. Worledge

2020 IEEE International Electron Devices Meeting (IEDM)（2020）

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关键词

optimal magnetic tunnel junction placement,lowest-cost integration scheme,MTJ stack,embedded STT-MRAM CMOS technology,eMRAM technology,embedded spin-transfer-torque MRAM technology,reference-cell sensing circuitry,electrode module,parametric analysis,switching voltage,endurance cycling,memory retention,temperature 400.0 degC,size 14.0 nm

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