A 16gb Sub-1v 7.14gb/S/Pin Lpddr5 Sdram Applying A Mosaic Architecture With A Short-Feedback 1-Tap Dfe, An Fss Bus With Low-Level Swing And An Adaptively Controlled Body Biasing In A 3rd-Generation 10nm Dram

2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)（2021）

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mosaic architecture,short-feedback sense amplifier,1-tap DFE,fully-source-synchronous bus scheme,low-level swing scheme,adaptive-body-bias scheme,DRAM process,adaptively controlled body biasing,low-power consumption,third-generation DRAM,mobile DRAM,5G communication,496-ball FBGA,FSS bus,decision feedback equalizers,limited package size,size 10.0 nm,voltage 1.0 V,storage capacity 16 Gbit

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