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A 24gb/S/Pin 8gb Gddr6 With A Half-Rate Daisy-Chain-Based Clocking Architecture And Io Circuitry For Low-Noise Operation

Kyunghoon Kim,Joo-Hyung Chae,Jaehyeok Yang,Jihyo Kang,Gang-Sik Lee,Sang-Yeon Byeon,Youngtaek Kim,Boram Kim, Dong-Hyun Kim,Yeongmuk Cho,Kangmoo Choi,Hyeongyeol Park,Junghwan Ji,Sera Jeong,Yongsuk Joo,Jaehoon Cha, Minsoo Park,Hongdeuk Kim,Sijun Park,Kyubong Kong,Sunho Kim,Sangkwon Lee,Junhyun Chun,Hyungsoo Kim,Seon-Yong Cha

2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)（2021）

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关键词
gddr6,clocking architecture,io circuitry,half-rate,daisy-chain-based,low-noise
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