CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)（2020）
Key words
ImageNet dataset,AlexNet,convolutional layers,nonlinearly quantized weights,array microarchitecture,memory-constrained edge devices,accumulator arrays,compressed neural networks,efficient hardware realization,CompAcc,simple array structure,TSMC technology,size 28.0 nm,power 15.6 mW
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