Single Event Upset for Monolithic 3-D Integrated 6T SRAM Based on a 22 Nm FD-SOI Technology: Effects of Channel Size and Temperature

The single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM with different channel sizes was investigated based on a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology over a temperature range from 210 K to 390 K. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and increasing the transistor size does not work in mitigating the SEU in M3D. It is also demonstrated that the SEU sensitivity of M3D 6T SRAM enhances with temperature rising after the incident of I-127 while it decreases after the striking of Bi-209. The reason can primarily be explained by the different influence ranges of striking heavy ions, which affect the ionized charge transport.