Frequency Generator for SoC Clocking

This work presents a compact voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28nm FD-SOI operates from 0.45V to 1.1V with measured jitter from 2.0% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57MHz 0.5V combined with the ability to perform fast frequency changes makes this circuit an alternative to PLLs for fast Dynamic Voltage and Frequency Scaling (DVFS) strategies in low power SoCs.