Modelling single-electron tunnelling circuits in VHDL-AMS

Abstract The single-electron tunnelling (SET) devices might be scaled down almost to the molecular level. SET devices can be faster and consume less power than comparable devices implemented in CMOS or bipolar technologies. This work presents VHDL-AMS macro-modelling techniques for the compact simulation of single-electron circuits. The macromodel of the single electron transistor, which is much more efficient than the corresponding Monte-Carlo calculations, is developed and can be a reasonably accurate tool for the simulation of complicated single-electron circuits.