A Wear-leveling Method for Balanced Multi-chip Life-time in NAND Flash-based Storage Devices

For high performance and large capacity, modern NAND flash-based storage devices (NFSDs) adopt a multi-chip architecture. However, a variety of workloads toward NFSDs induce uneven program/erase count of NAND flash memories (NFMs) which results in an imbalance of life-time of NFMs. In this paper, therefore, we propose a wear-leveling method that improves the life-time of NFSDs by redirecting write requests of an NFM having maximum erase count (Ec) to another NFM having minimum Ec. In this experiment, the proposed method reduces standard deviation of Ec and maximum Ec by 90% and 20%, respectively, which implies that the proposed method improves both the life-time of NFMs and NFSD significantly. Keywords—NAND flash memory, storage device, wear-leveling, multi-chip architecture