Hi-reI ASIC Design and Development - A Case Study

Hi-reI ASIC that functions in spacecrafts has to be optimized for performance, power and area, in addition to high reliability and quality standards, which demands adoption of state-of-the-art design methodologies and EDA tools for chip design. This paper explains the challenges in the development of multifunctional asynchronous ASIC and how these challenges were overcome by use of concurrent optimization methods with scenarios approach and physical aware synthesis methodology for quick timing closure. The DFT methodology adopted for realization of highly constrained form-fit device and ATPG to achieve the required coverage are also brought out with a case study.