A Reliability Overview of Intel's 10+Logic Technology

R. Grover, T. Acosta, C. AnDyke, E. Armagan,C. Auth,S. Chugh, K. Downes,M. Hattendorf,N. Jack,S. Joshi,R. Kasim, G. Leatherman, S-H Lee,C-Y Lin,A. Madhavan, H. Mao, A. Lowrie,G. Martin, G. McPherson,P. Nayak,A. Neale, D. Nminibapiel, B. Orr,J. Palmer,C. Pelto, S. S. Poon,I Post,T. Pramanik,A. Rahman,S. Ramey,N. Seifert,K. Sethi,A. Schmitz, H. Wu,A. Yeoh

2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)（2020）

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摘要

We provide a comprehensive overview of the reliability characteristics of Intel's 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel's FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

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关键词

cobalt interconnects,finFET,MIM capacitor,Pb-free packaging,thick metal

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