Advanced Thermal Modeling of IC – Package Interaction

A layout based finite element thermal convection model including detailed board tracing and packaging information is developed. A state-of-art 0.13-µm SiGe BiCMOS chip with embedded poly-resistors and thermal diodes are used as experimental validations of thermal modelling results. The designated thermal model demonstrates a high accuracy of less than 1.5 Celsius deviation from experimental results. And the layout based automatic generation of model geometry drastically reduces time consumption during model development and, moreover, paves the way for modelling of packages which possess even higher complexities.