A High-Linear Digital-to-Phase Converter in 40nm CMOS
ASICON（2019）
关键词
DPC,duty cycle corrector,phase interpolator,interpolation,phase interval,nonlinear weighting technology,systematic phase error,standard CMOS technology,high-linear digital-to-phase converter,delay-locked loop,DLL,size 40.0 nm,current 7.5 mA,voltage 1.1 V
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