Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high- ${k}$ /metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed.