A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

H. C. Lo,D. Choi,Y. Hu, Y. Shen,Y. Qi,J. Peng,D. Zhou, M. Mohan,C. Yong, H. Zhan, H. Wei,X. He,D. Kang, A. Sirman,Y. Wang, H. Zang, S. Y. Mun, A. Vinslava,W. H. Chen,C. Gaire, J. Liu,X. Dou, Y. Shi,P. Zhao,B. Zhu, A. Jha,X. Zhang, X. Wan, E. Lavigne, C. Kyono,M. Togo, J. Versaggi,H. Yu,O. Hu, J. G. Lee,S. B. Samavedam,D. K. Sohn

2018 IEEE Symposium on VLSI Technology（2018）

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关键词

FinFET,12LP,7.5T library,PPA

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