Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole

We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al 2 O 3 , HfO 2 on InGaAs shows a minimum defect density ∼0.2eV below the channel E C . By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.