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A 4 GHz Phase Locked Loop Design in 65 Nm CMOS for the Jiangmen Underground Neutrino Observatory Detector

N. Parkalian, M. Robens,C. Grewing,V. Christ,A. Kruth,D. Liebau,P. Muralidharan,D. Nielinger,C. Roth,U. Yegin,A. Zambanini, S. van Waasen

Journal of instrumentation（2018）

Cited 5|Views12
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Key words
Analogue electronic circuits,Front-end electronics for detector readout,VLSI circuits
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