Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.

Ivan Ratkovic,Oscar Palomar,Milan Stanic,Osman Sabri Unsal,Adrián Cristal,Mateo Valero

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2018）

引用 5|浏览57

暂无评分

摘要

The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating ...

查看译文

关键词

Vector processors,Registers,Clocks,Mobile communication,Benchmark testing,Computer architecture,Generators

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要