Impact of Wafer Thinning on Front-End Reliability for 3D Integration
IEEE International Reliability Physics Symposium(2016)
摘要
The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.
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关键词
3D integration,BTI,ESD,wafer thinning
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