FPGA Implementation of Scale Invariant Feature Transform

Scale Invariant Feature Transform is a competent algorithm for extracting unique features from images. The fact that features extracted are invariant to image scaling, translation, rotation and partially invariant to illumination changes makes it attractive in many computer vision applications involving mobile robots such as obstacle recognition, dynamic obstacle motion estimation, generating topological maps to enable autonomous navigation to name a few. The real challenge in such applications is to design an architecture that can provide for real time embedded computation of the features while optimizing area and power overhead. This paper presents the design of a System-on-Chip architecture for real time embedded computation of the features. The architecture exploits parallel and pipelined computational flow to achieve real time throughput while reducing the area and power overhead as compared to existing approaches. The entire hardware is implemented on a Xilinx Virtex-6 evaluation board.