32-Channel Self-Triggered ASIC for GEM Detectors

E. Atkin,I. Bulbakov,V. Ivanov,P. Ivanov,E. Malankin,D. Normanov, S. Petrovskiy,V. Shumikhin,A. Voronin,V. Samsonov

2017 IEEE 30TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL)（2017）

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Key words

readout channel,analog front-end,digital back-end,CR-RC shapers,differential threshold setup circuit,8 bit SAR ADC,digital peak detector,false peak detection,chip version,GBTx data processing board,output data,slow channels,fast channels,10 mW/channel,GEM detectors,multichannel readout chip,asynchronous architecture,32-channel chip,test results,chip building blocks,power consumption,clock data,detector capacitance,time stamp registration,SLVS receiver,SLVS transmitter,equivalent noise charge,power 1.5 mW,capacitance 50.0 pF,word length 8.0 bit

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