Timing margin analysis and Power measurement with DDR4 memory

DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems. The DDR4 signal interfaces operate up to a 3200 Mbps data rate and at 1.2 V. This is a higher frequency at a lower voltage, therefore lower power, than the third generation DDR3 DIMMs. The higher frequency and lower voltage results in decreased timing margins. The characterization of the timing margins and power usage is of significantly increased importance in DDR4. In this paper, a methodology for experimentally quantifying timing margins and power is applied at bounding voltage and frequency corners to plan, design, and architect HPC systems optimized for power consumption and with timing margin.