Clean Graphene Interfaces by Selective Dry Transfer for Large Area Silicon Integration

Here we present a very fast, selective mechanical approach for transferring graphene with low levels of copper contamination from seed wafers on which it was grown to target wafers for very large scale integration (VLSI) electronics. We found that graphene/copper or copper/silicon oxide delamination paths could be selected by slow and faster separation rates, respectively. Thus graphene can be transferred to a target wafer, either exposed or protected by the seed copper layer, which can later be removed by etching. Delamination paths were identified by SEM and Raman spectroscopy. The sheet resistance of the graphene produced by the two approaches was slightly higher than graphene transferred by a PMMA wet-transfer process, indicating reduced impurity doping, and the variation in the sheet resistance values was much lower. Copper contamination levels, quantitatively established by TOF-SIMS, were several orders of magnitude lower than the values for PMMA assisted transfer. In addition, we demonstrated that top-gated transistor devices from our mechanical, delamination transferred graphene exhibited superior transistor behavior to PMMA-assisted wet transfer graphene. The adhesion energy, strength and range of the interactions were quantitatively determined by nonlinear fracture analyses, and suggest that the roughness of the interface between graphene and copper plays an important role with implications for improvements in manufacturing processes.