An All-Hardware Implementation Of The Subpixel Refinement Stage In Sift Algorithm

This paper proposes an all-hardware architecture to perform the subpixel refinement operation in the scale invariant transform algorithm. Although the literature describes several hardware implementations of this algorithm, due to its complexity, most of them are based on simplifications of it. These implementations normally exclude the subpixel refinement stage, which, however, is an essential process to obtain accurate results in image matching applications. The architecture has been described in very high-speed integrated circuit hardware description language at register transfer level and synthesized on a Xilinx Zynq 7020 device. The latency of the proposed architecture to generate a refinement operation is 211 clock cycles, and the throughput achieved exploiting pipeline techniques is 64 cycles. The architecture uses fixed-point data representation and has been tested with images from known databases, yielding very good performance compared with the floating-point software implementation of the algorithm.